The evolution of the computer industry has been driven by the insatiable appetite of the consumer for ever increased speed and functionality. To meet this demand, computer designs rely on, among other innovations, two major techniques: increased frequency of operation for the circuitry comprising the computer system, and increased integration of functions onto a single integrated circuit (referred to as a very large scale integrated circuit, or VLSI chip).
These two techniques are interrelated. By placing more functionality onto a single integrated circuit, a greater frequency of operation for the communication paths between functional units can be achieved. Circuitry interconnect within a VLSI chip is typically one to two orders of magnitude faster than interconnections between physically distinct chips.
Increased density allows more functional units and their communication paths to be integrated onto a single VLSI chip as opposed to multiple chips inter-connected by a circuit board, MCM (multi-chip-module), or other means. Communication paths between functional units in an overall design are becoming an increasingly dominant factor in the overall performance of computing systems.
In addition, the progression of chip fabrication technology allows for higher frequency circuits and higher density circuits. This results in more functions being integrated onto a single VLSI chip and the circuits in these higher integration chips operating at ever increasing frequencies.
Increased density and higher frequency provide for increased performance and lower cost to the consumer. However, these design trends produce difficulties for chip designers. As the density of integration of circuits on a typical VLSI chip increases, chips become more complex functionally and therefore more prone to design errors. Prefabrication simulation and verification techniques are used to remove as many design faults as possible. Unfortunately, these techniques fail to produce a chip guaranteed to be free of design errors and, inevitably, debugging of a chip's design occurs after the chip has been fabricated and introduced into a system.
However, once a chip is fabricated, it is often impossible to directly observe the internal communication paths between functional units. These internal paths cannot be directly connected to test equipment to monitor their behavior. Access to these internal communication paths can be critical for debugging errors in a design.
In order to alleviate this problem, a number of chip pins are often dedicated to providing external visibility to one or more on-chip communication paths. The internal communication paths are connected to these dedicated pins which are then further connected to a connector providing an attachment point for test equipment. While this method does allow for monitoring of bus signals, it involves certain limitations.
The frequencies achieved by these on-chip interconnection paths can place an extreme burden on available test equipment. These frequencies can be difficult or impossible to monitor with the commercially available test equipment even though the internal communication path is exposed to the test equipment. Even in those cases where the frequency of operation is within the capabilities of available equipment, higher frequency operation requires the use of more expensive test equipment. Furthermore, as frequencies increase, the amount of functionality available from and number of signals that can be monitored simultaneously by the test equipment decreases.
It would, therefore, be a distinct advantage to have a method and apparatus that would allow for the monitoring, without loss of information, of internal communication paths of a VLSI chip at a lower frequency of operation. The present invention provides such a method and apparatus.